1. Field of the Invention
The present invention relates to a signal receiving circuit that receives, for example, signal bursts from a passive optical network (PON). More particularly, the invention relates to a level discrimination circuit of the type that automatically controls the threshold level used to determine the data values of the received signal.
2. Description of the Related Art
A circuit that receives optical signals has the general structure shown in FIG. 8, comprising a photodiode 1, a preamplifier 2, and a level discrimination circuit 3 that may also function as an automatic threshold control (ATC) circuit. The automatic threshold control feature is essential in a circuit that receives burst signals from a passive optical network. The threshold must be raised to the optimum level at the beginning of each burst, the optimum level being the threshold level that best enables the values of the received data to be correctly identified.
In the optical signal receiving circuit in FIG. 8, the optical signal is received by the photodiode 1 and thereby converted to a current signal. The preamplifier 2 converts the current signal to a voltage signal. The level discrimination circuit (or ATC circuit) 3 converts the voltage signal to a complementary pair of signals, referred to below as a positivephase signal and a negative-phase signal, that exhibit use of the optimum threshold level. Generally speaking, this is the level disposed at the midpoint of the voltage signal amplitude.
FIG. 9 shows the structure of a conventional level discrimination circuit. FIGS. 10A, 10B, 10C, 10D, and 10E show waveforms indicating signals and voltages in the conventional level discrimination circuit in FIG. 9. This conventional level discrimination circuit comprises a differential amplifier 10, a comparator 20, a pair of peak detection (DET) circuits 11, 12, a pair of summing circuits 13, 14, a reference voltage source 21 that generates a reference voltage Vref1, and a reference voltage source 22 that generates another reference voltage Vref 2. The peak detection circuits 11, 12, summing circuits 13, 14, and reference voltage sources 21, 22 constitute an offset compensation circuit. A level discrimination circuit of this type is described in, for example, U.S. Pat. Nos. 5,892,609 and 5,822,104 (and corresponding Japanese Unexamined Patent Application Publications No. 10-84231 and 08-293838).
In the level discrimination circuit in FIG. 9, the differential amplifier 10 receives a signal marked INPUT from the preamplifier 2 and reference voltage Vref1 from reference voltage source 21 (see FIG. 10A). The differential amplifier 10 generates a differential pair of voltage signals A1, NA1, outputs the positivephase voltage A1 to peak detection circuit 12 and summing circuit 13, and outputs the negativephase voltage NA1 to peak detection circuit 11 and summing circuit 14. As shown in FIG. 10B, positive and negative are with respect to Vref1.
The first peak detection circuit 11 senses the peak voltage of the negativephase voltage NA1, and outputs this negative-phase peak voltage NAP1 to summing circuit 13. The second peak detection circuit 12 senses the peak voltage of the positive-phase voltage A1, and outputs this positive-phase peak voltage AP1 to summing circuit 14 (see FIG. 10C).
Summing circuit 13 also receives the positive-phase voltage A1 and the reference voltage Vref 2 generated in reference voltage source 22. Summing circuit 13 adds the positive-phase voltage A1 and the negative-phase peak voltage NAP1, using the reference voltage Vref2 as a reference, and outputs the sum as a positive-phase voltage B1 to the comparator 20. Summing circuit 14 adds the negative-phase voltage NA1 and the positive-phase peak voltage AP1, using reference voltage Vref2 as a reference, and outputs the sum as a negative-phase voltage NB1 to the comparator 20 (see FIG. 10D).
The comparator 20 receives the positive-phase voltage B1 as its noninverting input and the negative-phase voltage NB1 as its inverting input and compares the level of voltage B1 with the level of voltage NB1, thereby discriminating the logic level of the received signal. The comparator 20 outputs a positive received data signal OUT and a negative received data signal NOUT with logic values of ‘1’ (High) or ‘0’ (Low), as shown in FIG. 10E.
Automatic threshold control is carried out in that regardless of the amplitude of the input signal (INPUT in FIGS. 9 and 10A), and regardless of its offset in relation to reference voltage Vref1, it is converted to a positive-phase voltage B1 and a negative-phase voltage NB1 having the same direct current (dc) level and amplitude but opposite logic. The ‘1’ and ‘0’ logic levels are clearly discriminated as equal but opposite differences between the offset-compensated positive-phase voltage B1 and the offset-compensated negative-phase voltage NB1.
FIG. 11 shows the structure of a conventional multistage level discrimination circuit using the same reference characters as in FIG. 9 for similar elements. This conventional multistage level discrimination circuit comprises a first-stage differential amplifier 10, a first-stage offset compensation circuit 30, a second-stage differential amplifier 15, a second-stage offset compensation circuit 31, and a comparator 20. The first-stage offset compensation circuit 30 and second-stage offset compensation circuit 31 both have the circuit configuration shown in FIG. 9. The second-stage offset compensation circuit 31 includes a pair of peak detection circuits 16, 17, a pair of summing circuits 18, 19, a comparator 20, and a reference voltage source 23 that generates a reference voltage Vref3. A multistage level discrimination circuit of this type is described in, for example, U.S. Pat. No. 5,892,609 (and corresponding Japanese Unexamined Pat. Application Publication No. 10-84231).
In the conventional multistage level discrimination circuit in FIG. 11, the positive-phase voltage B1 and the negative-phase voltage NB1 output from the first-stage offset compensation circuit 30 are input to the second-stage differential amplifier 15. The second-stage differential amplifier 15 receives the positive-phase voltage B1 as its non-inverting input and the negative-phase voltage NB1 as its inverting input, generates a positive-phase differential voltage A2 and a negative-phase differential voltage NA2, outputs the positive-phase voltage A2 to peak detection circuit 17 and summing circuit 18 of the second-stage offset compensation circuit 31, and outputs the negative-phase voltage NA2 to peak detection circuit 16 and summing circuit 19 in the second-stage offset compensation circuit 31.
In the second-stage offset compensation circuit 31, the first peak detection circuit 16 senses the peak voltage of the negative-phase voltage NA2, and outputs a negative-phase peak voltage NAP2 to summing circuit 18. The second peak detection circuit 17 senses the peak voltage of the positive-phase voltage A2, and outputs a positive-phase peak voltage AP2 to summing circuit 19.
Summing circuit 18 also receives the positive-phase voltage A2 and a reference voltage Vref3 generated by reference voltage source 23. Summing circuit 18 adds the positive-phase voltage A2 and the negative-phase peak voltage NAP2, using Vref3 as a reference, and outputs the sum as a positive-phase voltage B2 to the comparator 20. Summing circuit 19 adds the negative-phase voltage NA2 and the positive-phase peak voltage AP2, using Vref3 as a reference, and outputs the sum as a negative-phase voltage NB2 to the comparator 20.
The reference voltage Vref3 described above is generated with reference to the operating voltage range of the second-stage differential amplifier 15; the center voltage of the operating voltage range of the differential amplifier 15, for example, may be used as Vref3. The purpose of reference voltage Vref3 is to enable the summing circuits 18, 19 to operate within their dynamic range.
In a single-stage level discrimination circuit of the type shown in FIG. 9 the peak voltages AP1 and NAP1 may include a certain amount of error due imperfect operation of the peak detection circuits 11, 12. As a result, dc offset compensation is imperfect, causing the dc levels of the positive-phase and negative-phase voltages B1, NB1 to differ; that is, the High and Low levels of the positive-phase voltage B1 differ from the High and Low levels of the negative-phase voltage NB1.
Moreover, if the received burst optical signal includes bias light, then even if the peak detection circuits 11, 12 operate perfectly, a single-stage level discrimination circuit of the type shown in FIG. 9 cannot compensate completely for dc offset: the High and Low levels of the positive-phase voltage B1 will be higher than the High and Low levels of the negative-phase voltage NB1.
FIG. 12 shows how bias light is defined in a burst optical signal. FIG. 13 shows the general form of the gain characteristic of the pre amplifier 2 in FIG. 8, showing how the gain depends on the input current. FIG. 14 shows the waveform of the negative-phase signal output from the preamplifier 2 (the input signal received by the level discrimination circuit) when a burst optical signal including a large amount of bias optical power is received.
As shown in FIG. 12, bias light is the offset in optical power from the no-signal level between bursts to the Low signal level during a burst. Because of bias light, peak detection circuit 11 may be unable to detect the actual peak value of the negative-phase signal NA1 during a burst, detecting the no-signal level instead.
As shown in FIG. 13, the pre amplifier 2 has a gain saturation characteristic such that the gain decreases when the input current exceeds a certain value. Accordingly, if the bias light uses up a large amount of the linear region of the preamplifier 2, as may happen when the received burst optical signal includes a large amount of bias light the difference between the no-signal level (the detected peak) and the High level (the actual peak) of the negative-phase signal NA1 may be comparable to the difference between the High and Low levels, as shown in FIG. 14.
As a result, the duty cycle of the comparator output is degraded: the duration of periods in which the positive phase signal B1 output from summing circuit 13 has a lower voltage than the negative-phase signal NB1 output from summing circuit 14 is significantly shortened, so that in the output of the comparator 20, the Low (“L”) logic-level periods are markedly shorter than the High (“H”) logic-level periods, as illustrated in FIG. 15. In the extreme case, the positive-phase signal voltage never goes below the negative-phase signal voltage, and the comparator output always indicates the High logic level, as illustrated in FIG. 16.
A multistage level discrimination circuit of the type shown in FIG. 11 mitigates this problem by amplifying the difference between the positive-phase voltage B1 and the negative-phase voltage NB1. In the amplified negative-phase signal NA2, the difference between the High and Low levels is enhanced, so the detected peak value NAP2 is closer to the actual peak value. If the amount of bias light is not too great, the detected peak value NAP2 will be equal to the actual peak value, in which case the second-stage positive-phase voltage and negative-phase signals B2, NB2 will have the same dc level and correct data output signals will be obtained from the comparator 20.
If an optical signal burst including a large amount of bias optical power is received, however, the second-stage negative-phase peak value NAP2 may still differ significantly from the actual peak value, so the problems noted above remain. That is, the duty cycle of the comparator output is degraded (FIG. 15), or in the extreme case, the Low logic level disappears (FIG. 16). In FIG. 15, it becomes difficult to sample the Low logic level accurately. In FIG. 16, it becomes impossible; the received data signal is completely hidden.
Conventional methods for accurately receiving an optical signal burst including bias light are described in a Document A (by M. Nakamura, N. Ishihara, and Y. Akazawa entitled “A 156 Mb/s CMOS Optical Receiver ICs for Burst-mode Transmission”, 1997, 8th International Workshop on Optical/Hybrid Access Networks Conference Proceedings Poster Session p. 12) and a Document B (by K. Takeda et al. entitled “FSAN taio 156 Mb/s 3.3V basuto hikari jushinki yo 1 chippu LSI”(1 chip LSI for a 156 Mb/s 3.3V burst optical receiver for FSAN), 1999 IEICE General Conference, SC-12-3). In the methods described in Documents A and B, the feedback resistance in the preamplifier 2 in FIG. 8 is switched for each optical signal burst, thereby avoiding the use of the saturation region of the gain characteristic shown in FIG. 13 and preventing a large dc offset in the signal output from the preamplifier 2.
In the conventional methods described in Documents A and B, however, another resistor and a switch have to be added to the circuit in order to switch the feedback resistance, and an extra capacitor has to be added on the input terminal of the preamplifier 2, so the frequency characteristic and the noise characteristic in the preamplifier 2 are significantly degraded. This lowers the performance characteristics of the burst optical signal receiving circuit, degrades the receiving sensitivity, and narrows the receiving dynamic range. These problems render the methods described in Documents A and B impractical.